(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to improve the roughness of metal deposition on low-k material.
(2) Description of the Prior Art
In the manufacturing of semiconductor devices, the industry is continuously striving to improve device performance by reducing device size while at the same time reducing the device cost. The reduction of device feature size to the micron and sub-micron scale has succeeded in improving device performance while also meeting cost objectives. Important parameters in the device manufacturing are internal resistances and capacitances, these potentially performance-limiting parameters frequently require sophisticated methods of control and manufacturing that can contribute significantly to device cost. The control of these parameters also frequently leads to methods of layer deposition and surface control that manipulate and influence these surfaces on the molecular level. Underlying layer surface roughness for instance can have a significant impact on the smoothness of the overlying layer and therefore have a significant impact on the resistivity of this overlying layer. Micro-miniaturization has in many instances been accomplished by advances in several semiconductor fabrication disciplines, including photolithography and Reactive Ion Etching (RIE). The use of more sophisticated exposure cameras as well as the use of more sensitive photoresist materials have allowed sub-micron images to be routinely produced in photoresist materials. In addition, similar advances in dry etching apparatus and procedures have allowed the sub-micron images in photoresist to be successfully transferred to underlying materials that are used for the fabrication of silicon chips.
In the evolution of integrated circuit chips, scaling down feature size improves performance of internal devices in the chips by increasing the speed and functional capability of the devices. As the devices get smaller, however, their performance becomes more heavily dependent on the interconnections between them. Likewise, as the number of devices per chip increases, the area required to route the interconnect lines exceeds the area occupied by the devices. This normally leads to integrated circuit chips with multilevel interconnect schemes.
In the creation of metal interconnect lines and contact or via plugs, copper is often the preferred metal due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper however readily diffuses into commonly used insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This can lead to severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required.
In a typical construction of for instance a damascene structure, a diffusion barrier is deposited over the inside of the opening for this structure. In many applications, a seed layer is then deposited over the barrier layer over which a layer of copper, for copper damascene structures, is deposit. The microstructure of the (electroplated) copper is highly dependent on the characteristics of the underlying barrier and seed layers. A smooth and strongly textured copper seed layer is required to assure that the overlaying layer of copper (that makes up the damascene plug) is highly textured and has a large grain content. These latter properties are required to enhance the reliability of the damascene structure. If, in the device feature size in the deep sub-micro range, a fine grain structure is created in the deposited layer of copper, the electromigration lifetime of the deposited layer of copper will be degraded. In trenches, the electroplated copper has a relatively large grain structure resulting in no degradation of the copper reliability in deep trenches. The electromigration performance of electroplated copper is therefore superior to that of CVD copper especially for deep sub-micron Damascene interconnects.
As semiconductor devices continue to be scaled down, interconnect delay becomes the performance barrier for high-speed silicon integrated circuits (IC's). The increased interconnect delay will reduce device speed and exaggerate the problem of high cross talk and power dissipation. Low resistivity metal (Cu) and low dielectric constant insulator are the potential candidates to reduce the increased interconnect delay. Thus, Cu interconnect for backend-of-line (BEOL) has been proposed to improve chip performance. It is desired to integrate Cu and low-k dielectric to further improve the performance. Organic polymers are generally known to exhibit a lower dielectric constant than oxide and nitride, and thus are considered as candidates for deep sub-micron inter-metal dielectric. Several annealing techniques such as ion implantation and plasma treatment have been found to be able to improve spin-on dielectric properties. Recently, a novel electron beam (e-beam) curing method has been adopted to improve spin-on-glass (SOG) properties and to prevent plasma damage during the step of via opening. The high-energy electrons penetrate the dielectric film and transfer the electron energy to the dielectric material. It has been found that e-beam cured SOG has superior performance when compared with SOG that has been thermally cured.
In a number of case studies the effect of grain size in narrow interconnects has been studied, specifically the impact that grain size has on Mean Time To Failure (MTTF) and Electromigration Induced failure. It has been found that, as the ratio of the line width to the grain size decreases, MTTF decreases to a minimum and then increases exponentially. Electromigration Induced failure increases continuously. Another study has reported on the impact on electromigration of (111) or (200) textured CVD copper films. This study has found that the electromigration lifetime of (111) CVD copper is about four times longer than the electromigration lifetime of (200) CVD copper, this under equal conditions of activation energy (about 0.8 eV) for both types of textured CVD Cu films. The above-cited studies have been listed in the enclosed list of patents and articles.
Chung- I Chang, et. al., "A Novel E-Beam Treatment Technique To Improve TaN Barrier Properties for Dual Damascene Cu And Low-K Integration."
Wong et al., "Barrier/Seed Layer Requirements for Copper Interconnects".
Changsup Ryu, et al., "Electromigration of Submicron Damascene Copper Interconnects", pp. 156-157, 1998 Symposium n VLSI Technology Digest of Technical papers.
J. Cho, et. al., "Grain Size dependence of electromigration induced failures in narrow interconnects", Appl. Phys. Lett. 54(25), Jun. 19, 1989, pp. 2577-2579.
Changsup Ryu, et al., "Effect of Texture on the Electromigration of CVD Copper", IEEE 9/1997 pp. 201 to 205.
U.S. Pat. No. 4,537,811 (Nablo) shows an E-beam process for e-beam curing of coatings.
U.S. Pat. No. 4,543,268 (Sidney et al.) shows an E-beam adhesion promoting treatment.
U.S. Pat. No. 4,594,262 (Kreil et al.) discloses an e-beam adhesion promoting treatment of polyester film base.